In this issue, I’ll cover the following:
- Update on Changes to LE Modules
2. Feedback From Our Newest Class
3. Update on JES2 Re-Assembly
4. SHARE Conference is August 10-15
5. Corrections to APAR Numbers
6. HDS Announces New Processors
7. New RMF Home Page URL
8. Signature Tag Lines
- Update on Changes to LE Modules
In Cheryl’s List #4, I included a comment from Tom Ross, COBOL Family Development, in which he stated that some date simulators ZAP an LE module, and that you should keep a separate copy of LE for production.
Anne White from ISOGON Corporation which markets one of the mentioned products, TICTOC, asked me to point out that TICTOC’s documentation has always recommended that the zapped module be placed in a separate, non-production load library. Therefore, testing and implementation of TICTOC according to their documentation should present no conflict with IBM’s support of LE.
- Feedback From Our Newest Class
We’ve just finished the first new “Advanced OS/390 Performance & Capacity Planning” class. It was given to a group of thirty-nine students (including people from Spain, Venezuela, Korea, Thailand, Austria, Australia, and Canada), and was held in sunny Sarasota. Judging from the comments received, it was a success. Here are some student remarks:
“This is the only class where I got a very practical approach to capacity planning and performance. I was able to go back to my site and immediately identify/recommend/improve performance and be prepared to intelligently evaluate the impact of new products/releases, etc.”, Ken Usen, United Parcel Service
“Economic value far outweighs any other I’ve been in from other vendors”, Gerald Szilagyi, Chrysler Information Services
“You have a wonderful presence, you explain most things in such a way that everyone could understand. I learned a lot.”, Dan Tartaglia, Amdahl
- Update on JES2 Re-Assembly
On page 6 of the 1997, No. 1 issue of the TUNING Letter, I discussed WSC Flash #9638 which pointed out the need to either re-assemble all JES2 modules in OS/390 R2 with SPLEVEL=6 or assemble and link all of your usermods and exits with SPLEVEL=5. Stan DeOrsey, Manager of OS/390 JES2/SDSF Development, pointed out that APAR OW25198 was designed to eliminate that problem by allowing SPLEVEL=5 and SPLEVEL=6 to co-exist. Eric Koroluk, from Alberta Public Works Supply and Services, said that he applied the APAR and was able to install their exits with absolutely no problems or additional assemblies.
- SHARE Conference is August 10-15
Bob Shannon, Programart (and SHARE MVS Cluster Manager) pointed out that on page 25 of the 1997, No. 1 issue, we incorrectly listed the next SHARE conference with an August 17-18 date. It’s actually August 10-15 in Atlanta. I’ll be giving a presentation on OS/390 Key Indicators and A Quickstart Policy Update. We’ll also have a booth at the SHARE Technology Exchange. Hope to see you there!
- Corrections to APAR Numbers
Brian Currah of BDC Computer Services found a couple of typos in our 1997, No. 1 issue. The first is on page 18 under the Bit Bucket entry. APAR OY24778 should be OW24778. This APAR was the actual fix (the other two were closed as canceled and SUG). The list of APARs for DFSMS enhancements on page 19 included APAR OW2029, which should really be OW20929.
Brian also pointed out that APAR OW21842 should also be included in the list. The last two APARs, OW24857 and OW25113, are actually PE APARs against the PTF, UW34547, which contains the first set of APARs. Brian adds that additional APARs report problems which occur after UW34547 has been applied. They are: OW26358 (SMF type 30s have block size of zero for Joblib/Steplib), OW24780, OW24852, OW24886, and OW25230.
Since this set of APARs/PTFs is closely tied to the OS/390 R3 I/O priority management, it’s important for users to apply and understand these fixes before attempting to use the new I/O priority velocity.
Eagle-eye Brian also noted that Flash #9652 (RAMAC and R0), as mentioned on page 16 in Session 2500 by Kathy Walsh, is not available for Internet or Resolve customers. Kathy said that for some reason it had been removed, and she’s working to have it replaced.
Thanks very much, Brian!
- HDS Announces New Processors
On May 13, HDS announced nine new Skyline models and seventeen new CMOS machines. The Skyline models consist of three low-end models (80+ MIPS uni) and six high-end models that provide a 25% increase in speed. Their largest 8-way machine provides close to 1000 MIPS (as compared to IBM’s 10-way 9X2 that’s 459 MIPS). Most of the new CMOS Pilot models are based on a uni-processor speed of over 60 MIPS.
This is pretty exciting news since many installations have been wanting to obtain the benefits of CMOS processors (significant savings on energy, maintenance, and floorspace), but have workloads that are unable to use the slower 45 MIPS processors. Now that CMOS can almost match the largest bipolar (with the exception of Skyline), most installations will be able to take advantage of the CMOS savings.
Another major piece of the announcement were the value-added facilities provided by the new HDS processors:
- HDS RTX Time Machine and HDS RTX Time Warp – two products that address Year 2000 compliance by providing a hardware feature for identifying problem code and providing help with testing Year 2000 changes.
- HDS HiSolve-2000 – previously announced in June 1996, this complements the previous two products with a set of services to help evaluate the impact, risk, and actions needed to meet the Year 2000 challenge.
- HDS Time Traveler – this is a feature of the HDS 7700 Scalable Array storage subsystem that provides the ability to non-disruptively copy production data (locally or remotely) for backups, Year 2000 testing, and application development.
- ISM Capacity & Performance Manager – all new Pilot machines will be packaged with ISM/CP from The Information Systems Manager, Inc. ISM/CP provides a comprehensive set of reports and tools to provide capacity planning and performance data. I included a product highlight of ISM/CP in our Jan/Feb 1995 issue because I thought so highly of the product.
I think what’s most interesting about this announcement is that it’s a step beyond the traditional hardware solution of providing clones of IBM machines. The additional hardware and software facilities provide extra value that helps differentiate the HDS offering from the other vendors’ offerings. It will be interesting to see what IBM and Amdahl will bring to the table next.
IBM is expected to announce their new 60+ MIPS CMOS processors within the next few weeks. At that time, HDS will most likely announce “parity” between their CMOS processors and IBM’s. That means that the processor groups, MSUs, and MIPS for the HDS processors will change, if necessary, to match those of IBM’s.
For those users of our CPU Chart, I’ve included the preliminary (estimated) processor groups and MSUs for each of the new processors, as well as some other updates. Subscribers to “Cheryl Watson’s TUNING Letter” may obtain the preliminary MIPS estimates for all these processors by sending an email to Doni Richardson firstname.lastname@example.org including either the company name and address or the subscriber’s name. The estimates will also be included in the next newsletter.
(Some people feel that a major benefit of subscribing to our TUNING Letter is receiving our extensive CPU Chart and updates. The CPU Chart contains CPU models from all three vendors, the number of CPUs, average, min, and max MIPS, MIPS per CPU, processor group, MSUs, and version code. A recent addition even provides the processors groups in descending order and MSUs for easy evaluation of options when trying to size a new machine.)
The following material has been provided by HDS as preliminary (note that I said “preliminary”!) data:
Model # CPUs Proc Grp MSUs
Pilot 14S 1 38 6
Pilot 15S 1 38 8
Pilot 24S 2 40 11
Pilot 25S 2 40 15
Pilot B5 10 80 64 (similar to IBM’s RY4)
Pilot 17 1 40 11
Pilot 26 2 50 19
Pilot 27 2 50 21
Pilot 36 3 60 26
Pilot 37 3 70 30
Pilot 46 4 70 33
Pilot 47 4 80 37
Pilot 57 5 80 48
Pilot 67 6 80 57
Pilot 77 7 80 62
Pilot 87 8 80 67
Pilot 97 9 80 71
Pilot A7 10 80 75
Skyline 211 2 60 27
Skyline 213 2 70 36
Skyline 313 3 80 53
Skyline 115 1 60 22 (was model 11)
Skyline 215 2 80 41 (was model 21)
Skyline 315 3 80 60 (was model 31)
Skyline 325 3 80 60 (was model 32)
Skyline 415 4 80 76 (was model 41)
Skyline 425 4 80 76 (was model 42)
Skyline 525 5 IMLC 92 (was model 52)
Skyline 625 6 IMLC 106 (was model 62)
Skyline 725 7 IMLC 120 (was model 72)
Skyline 825 8 IMLC 134 (was model 82)
Skyline 417 4 IMLC 95
Skyline 427 4 IMLC 95
Skyline 527 5 IMLC 114
Skyline 627 6 IMLC 131
Skyline 727 7 IMLC 151
Skyline 827 8 IMLC 168
- New RMF Home Page URL
Robert Vaupel, of RMF development, pointed out that RMF has a new home page URL. You can find their home page at http://www.s390.ibm.com/rmf. If you’re interested in seeing any of the new RMF facilities, such as the RMF Spreadsheet Reporter or the new Performance Monitoring for OS/390, you can find newsletters on the new facilities and a list of conferences where you can see the products demonstrated.
- Signature Tag Lines
Signature tag lines in Internet email can be fun and add a smile to your day. Here are some that I’ve found amusing.
All wiyht. Rho sritched mg kegtops awound?
All opinions expressed are my own, unless given to me by my wife.
Isn’t it great how in MVS, we don’t get messages like ‘DB2 caused a general protection fault in module
MVS at offset 00000:62347, your application will be terminated’ every half hour?
“PMS + dyslexia = SMP”
I speak for myself & my dogs only.
My employer agrees with me but doesn’t know it.
The reason that God was able to create the world in seven days is that He didn’t have to worry about the installed base.
My employer may or may not agree. Does it matter?
There are many collections of signature tag lines on the Web. I thought you might find these two humorous:
There are many collections of signature tag lines on the Web. Here’s a good one:
That’s all for now. Stay tuned!